The present invention relates to integrated circuits and semiconductor device fabrication and, more specifically, to structures for interconnects and methods for forming interconnects.
An interconnect structure may be used to electrically connect device structures fabricated on a substrate by front-end-of-line (FEOL) processing. A back-end-of-line (BEOL) portion of the interconnect structure includes metallization formed using a dual damascene process in which via openings and trenches etching in a dielectric layer are simultaneously filled with metal to create a metallization level. The lowest metal level of the BEOL interconnect structure may be coupled with the device structures by features, such as contacts, formed prior to BEOL processing using metallization formed by middle-of-line (MOL) processing.
Improved structures for interconnects and methods for forming interconnects are needed.